1. Field of the Invention
The present invention relates to an IP stream transmitting/receiving system, an IP stream receiving device and a receiving processing timing synchronization method used for the same, and specifically to timing synchronization of receiving processing of the IP (Internet Protocol) stream.
2. Description of the Related Art
When a video stream, an audio stream or the like are transmitted/received in real-time on the IP network or the like, the UDP (User Datagram Protocol) packet is generally used. For the video stream and the audio stream, coded data represented as the MPEG2 (Moving Picture Experts Group-2)-TS (Transport Stream) or the uncompressed (PCM: Pulse Code Modulation) data and the like are used.
The synchronizing timing in receiving the IP stream (for example, TS time stamp) is provided on the protocol defined at the level higher than the UDP [for example, RTP (Real-time Transport Protocol)]. In such a case, as the IP stream, a case in which an RTP header is added as shown in FIG. 8A and a case in which a unique header is added as shown in FIG. 8B are known.
The IP stream shown in FIG. 8A includes “IP header”, “UDP header”, “RTP header” and “PAYLOAD (video, audio and the like)” with synchronizing timing being inserted in the “RTP header”. The IP stream shown in FIG. 8B includes “IP header”, “UDP header”, “unique header” and “PAYLOAD (video, audio and the like)” with synchronizing timing being inserted in the “unique header”. The top of the sequence number of the RTP header or a synchronizing flag for the unique header can be used in the place of the abovementioned synchronizing timing.
FIG. 9 shows an exemplary configuration of a device for receiving an IP stream. In FIG. 9, a video/audio receiving device 3 includes an UDP/IP receiving circuit 31 for receiving an IP packet from the IP network 100, an FEC (Forward Error Correction) decoding circuit 32 for performing FEC decoding from the received IP packet, and a video/audio decoding circuit 33 for decoding the TS packet which has been FEC decoded and error corrected to output a video/audio.
The synchronizing timing of the IP stream (receiving processing timing) is required for the FEC decoding and the like (block processing, framing processing) immediately after the reception of the IP stream. Here, a block refers to a set of n TS packets. In the FEC decoding, error correction to be described later is performed and the lost TS packet is reconstructed (for example, see Japanese Patent Laid-Open No. 2005-210219).
The abovementioned synchronizing timing is controlled by adding the arrival time of the leading byte of the TS packet as the TS time stamp immediately before the packet is transmitted at the transmitter and reproducing the TS time stamp at the receiver with the FIFO (First In First Out) or the like so that, referring to the time stamp information added to the top of the TS packet, the packet interval becomes the same as that at the time when the packet is transmitted (when the TS time stamp is added). Here, the time stamp information is represented by the 27 MHz, the count value 32 bit. That is generally called as a time-stamped TS (TTS).
FIG. 10 shows an example of case of adding the TS time stamp. In the case shown in FIG. 10, assuming that the TS time stamp of a TS packet #0 is t0, the TS time stamp of a TS packet #1 is t1, and a time when the TS packet #0 is read from the FIFO is tA, the timing tB for reading the TS packet #1 from the FIFO is calculated by the following equation.tB=tA+(t1−t0)
In the FEC processing, the “linear code” such as the Reed Solomon code or the LDPC (low density parity check) code can be generally used. Hereinafter, error correction operation at the packet level (one packet=one bit in a code word) will be described by taking the LDPC code as an example.
First, when the packets “0” to “6” are input in the FEC processing, the redundant packets “7” to “9” are created based on a preset check matrix as shown in FIG. 11. In this case, the redundant packet “7” is calculated by the exclusive OR of the packet “1”, the packet “3” and the packet “5”. The redundant packet “8” is calculated by the exclusive OR of the packet “2”, the packet “4” and the packet “6”. The redundant packet “9” is calculated by the exclusive OR of the packet “0”, the packet “3” and the packet “6”.
At the receiver, when the IP stream, in which the redundant packets “7” to “9” are added and the packets “0”, “3” and “6” are lost as shown in FIG. 12, is received, an error list is created as “0” is written at the place of the received packet based on the sequence number of the received packet. Here, an initial value of the error list is assumed as “1”. As the packets “0”, “3” and “6” are lost in this case, the error list will be “1001001000”.
When the error list and the check matrix are matched, the error list is read from the top in order and if a weight (‘1’) exists in a “column” corresponding to ‘1’ of the error list, the weight is defined as the “error weight” (encircled number). Then the number of the error weights is counted for each row (the number of row error weights).
In the example shown in FIG. 12, the number of the row error weights in the first row of the check matrix is “1”, the number of the row error weights in the second row of the check matrix is “1”, and the number of the row error weights in the third row of the check matrix is “3”. It is determined that the first and the second rows of the check matrix can be recovered based on the result. Then the lost packets “3” and “6” are recovered by the exclusive OR of the packets corresponding to weights (‘1’) other than “error weight” at each of the first and the second rows in the check matrix. In this case, the lost packet “3” is recovered by exclusive OR of the packet “1”, the packet “5” and the packet “7”. The lost packet “6” is recovered by exclusive OR of the packet “2”, the packet “4” and the packet “8”.
The abovementioned processing is called “search” in the FEC processing. By the first “search”, the lost packets “3” and “6” are recovered. Then in the FEC processing, the second “search” is performed. As the lost packets “3” and “6” are recovered at that time, the error list is updated by writing “0” in the place of the recovered packets “3” and “6” as shown in FIG. 13.
Also at the second “search”, the error list and the check matrix are matched, the error list is read from the top in order and if a weight (‘1’) exists in a “column” corresponding to ‘1’ of the error list, the weight is defined as the “error weight” (encircled number). Then the number of the error weights is counted for each row (the number of row error weights).
In the example shown in FIG. 13, the number of the row error weights in the first row of the check matrix is “0”, the number of the row error weights in the second row of the check matrix is “0”, and the number of the row error weights in the third row of the check matrix is “1”. It is determined that the third row of the check matrix can be recovered based on the result. Then the lost packet “0” is recovered by the exclusive OR of the packets corresponding to weights (‘1’) other than “error weight” at the third row in the check matrix. In this case, the lost packet “0” is recovered by exclusive OR of the packet “3”, the packet “6” and the packet “9”.
As mentioned above, the error correction such as the LDPC repeatedly performs searching any number of times until no pattern, to which error correction can be applied, is found. However, because the error correction processing time such as for the LDPC processing is limited in real-time processing as shown in FIG. 14 (1 FEC block time), the correction start time of each FEC block is required to be defined. In such a case, the correction start time of each FEC block is determined by the FEC outputting timing (=TS time stamp reproducing timing).
In FIG. 14, for the FEC processing, the FEC input, the FEC correction and the FEC output are sequentially performed. That is, first, the processing at the FEC input #1 is performed. When the processing at the FEC input #1 is finished, the processing at the FEC input #2 and the processing at the FEC correction #1 are performed. When the processing at the FEC input #2 is finished, the processing at the FEC input #3, the processing at the FEC correction #2 and the processing at the FEC output #1 are performed. As such, in the FEC processing, each processing of the FEC input, the FEC correction and the FEC output is sequentially performed.
If the abovementioned device for receiving an IP stream performs the error correction such as the LDPC, searching is repeated any number of times until no pattern, to which error correction can be applied, is found. However, because it has the next correction start timing for the next block, its error correction processing time is limited, particularly when the processing is performed in real-time.
When reception of the IP stream is in an unstable state due to the network jitter, the packet order changing, the packet loss or the like, it is difficult to perform the error correction in a stable and effective manner. Specifically, the error correction processing time may not be sufficiently afforded. If a time for receiving the prior block is extended due to the network jitter, the error correction processing time of the block subsequent to the prior block cannot be sufficiently afforded. If the error correction processing time is shortened, the number of repeats of the search is decreased. That deteriorates the error correction efficiency.